Global Corpus
Collection
6 items • Updated • 3
repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
0015/esp_rlottie | 19,929 | rlottie/src/vector/pixman/pixman-arm-neon-asm.S | /*
* Copyright © 2009 Nokia Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, pub... |
0BAB1/HOLY_CORE_COURSE | 1,138 | 1_fpga_edition/fpga/test_programs/test.s | # Blink leds
#
# Assembly to blink LEDs once / second in a counter motion.
# Uses a cache miss to write back.
#
# BRH 11/12
.section .text
.align 2
.global _start
start:
# Initialization
lui x6, 0x2 # 00002337 Load GPIO base address x6 <= 0x00002000
lui x7, 0x2 # same for x... |
0BAB1/HOLY_CORE_COURSE | 1,037 | 1_fpga_edition/fpga/test_programs/hello_world/hello.s | .section .text
.align 1
.global _start
_start:
# Setup uncached MMIO region from 0x2000 to 0x2FFF
lui x6, 0x2 # x6 = 0x2000
lui x7, 0x2
ori x7, x7, -1 # x7 = 0x2FFF
csrrw x0, 0x7C1, x6 # MMIO base
csrrw x0, 0x7C2, x7 # MMIO limit
# UARTLite base... |
0BAB1/HOLY_CORE_COURSE | 7,408 | 1_fpga_edition/fpga/test_programs/I2C_pressure/pressure.s | # HOLY CORE PROGRAM
#
# Read the I2C BMP280 sensor and print value to UART as hexadecimal
#
# BRH - 30/05/25
.section .text
.align 1
.global _start
# NOTES :
# 100h => Control
# 104h => Sattus
# 108h => TX_FIFO
# 10Ch => RX_FIFO
# I²C READ (from BMP280 datasheet)
#
# To be able to read registers, first the register ... |
0BAB1/HOLY_CORE_COURSE | 8,187 | 2_soc_software_edition/tb/holy_core/test.s | # HOLY_CORE BASIC TEST PROGRAM
#
# This program tests basic behavior of the core.
# This test does not ensure compliance but rather
# serve as a quick reference to know if
# the design compiles and if a change
# broke the basic CPU behavior.
#
# BRH 7/25
.section .text
.global _start
_start:
# DATA ADDR STORE
... |
0intro/9hist | 8,780 | alphapc/l.s | #include "mem.h"
#define SP R30
#define HI_IPL 6 /* use 7 to disable mchecks */
TEXT _main(SB), $-8
MOVQ $setSB(SB), R29
MOVQ R29, R16
CALL_PAL $PALwrkgp
MOVQ $mach0(SB), R(MACH)
MOVQ $(BY2PG-8)(R(MACH)), R30
MOVQ R31, R(USER)
MOVQ R31, 0(R(MACH))
MOVQ $edata(SB), R1
MOVQ $end(SB), R2
clrbss:
MOVQ R31, ... |
0intro/9hist | 2,936 | alphapc/memmove.s | #define QUAD 8
#define ALIGN 64
#define BLOCK 64
TEXT memmove(SB), $0
MOVL from+4(FP), R7
MOVL n+8(FP), R10
MOVQ R0, R6
CMPUGE R7, R0, R5
BNE R5, _forward
MOVQ R6, R8 /* end to address */
ADDL R10, R6, R6 /* to+n */
ADDL R10, R7, R7 /* from+n */
CMPUGE $ALIGN, R10, R1 /* need at least ALIGN bytes */
... |
0intro/9hist | 10,389 | mtx/l.s | #include "mem.h"
/* use of SPRG registers in save/restore */
#define SAVER0 SPRG0
#define SAVER1 SPRG1
#define SAVELR SPRG2
#define SAVEXX SPRG3
/* special instruction definitions */
#define BDNZ BC 16,0,
#define BDNE BC 0,2,
#define TLBIA WORD $((31<<26)|(307<<1))
#define TLBSYNC WORD $((31<<26)|(566<<1))
/* on so... |
0intro/9hist | 1,476 | mtx/inb.s | #include "mem.h"
#define BDNZ BC 16,0,
#define BDNE BC 0,2,
TEXT inb(SB), $0
OR $IOMEM, R3
MOVBZ (R3), R3
RETURN
TEXT insb(SB), $0
MOVW v+4(FP), R4
MOVW n+8(FP), R5
MOVW R5, CTR
OR $IOMEM, R3
SUB $1, R4
insb1:
MOVBZ (R3), R7
MOVBU R7, 1(R4)
BDNZ insb1
RETURN
TEXT outb(SB), $0
MOVW v+4(FP), R4
OR $IOME... |
0intro/9hist | 18,182 | bitsy/l.s | #include "mem.h"
/*
* Entered here from Compaq's bootldr with MMU disabled.
*/
TEXT _start(SB), $-4
MOVW $setR12(SB), R12 /* load the SB */
_main:
/* SVC mode, interrupts disabled */
MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R1
MOVW R1, CPSR
/* disable the MMU */
MOVW $0x130, R1
MCR CpMMU, 0, R1, C(CpControl), C... |
0intro/9hist | 2,349 | bitsy/bitsyreset.s | #include "mem.h"
// Bitsy development board uses two banks: KM416S4030C,
// 12 row address bits, 8 col address bits
// Bitsy uses two banks KM416S8030C, 12 row address bits,
// 9 col address bits
// Have to set DRAC0 to 14 row bits or else you only get 8 col bits
// from the formfactor unit configuration regi... |
0intro/9hist | 1,493 | pc/ptclbsum386.s | TEXT ptclbsum(SB), $0
MOVL addr+0(FP), SI
MOVL len+4(FP), CX
XORL AX, AX /* sum */
TESTL $1, SI /* byte aligned? */
MOVL SI, DI
JEQ _2align
DECL CX
JLT _return
MOVB 0x00(SI), AH
INCL SI
_2align:
TESTL $2, SI /* word aligned? */
JEQ _32loop
CMPL CX, $2 /* less than 2 bytes? */
JLT _1dreg
SUB... |
0intro/9hist | 1,527 | pc/apmjump.s | /*
* Far call, absolute indirect.
* The argument is the offset.
* We use a global structure for the jump params,
* so this is *not* reentrant or thread safe.
*/
#include "mem.h"
#define SSOVERRIDE BYTE $0x36
#define CSOVERRIDE BYTE $0x2E
#define RETF BYTE $0xCB
GLOBL apmjumpstruct+0(SB), $8
TEXT fortytwo(SB),... |
0intro/9hist | 20,868 | pc/l.s | #include "mem.h"
#define PADDR(a) ((a) & ~KZERO)
#define KADDR(a) (KZERO|(a))
/*
* Some machine instructions not handled by 8[al].
*/
#define OP16 BYTE $0x66
#define DELAY BYTE $0xEB; BYTE $0x00 /* JMP .+2 */
#define CPUID BYTE $0x0F; BYTE $0xA2 /* CPUID, argument in AX */
#define WRMSR BYTE $0x0F; BYTE $0x30 /... |
0intro/9hist | 3,037 | pc/apbootstrap.s | #include "mem.h"
#define NOP BYTE $0x90 /* NOP */
#define LGDT(gdtptr) BYTE $0x0F; /* LGDT */ \
BYTE $0x01; BYTE $0x16; \
WORD $gdtptr
#define FARJUMP16(s, o) BYTE $0xEA; /* far jump to ptr16:16 */ \
WORD $o; WORD $s; \
NOP; NOP; NOP
#define FARJUMP32(s, o) BYTE $0x66; /* far jump to ptr32:1... |
0intro/libtask | 5,926 | asm.S | /* Copyright (c) 2005-2006 Russ Cox, MIT; see COPYRIGHT */
#if defined(__FreeBSD__) && defined(__i386__) && __FreeBSD__ < 5
#define NEEDX86CONTEXT 1
#define SET setmcontext
#define GET getmcontext
#endif
#if defined(__OpenBSD__) && defined(__i386__)
#define NEEDX86CONTEXT 1
#define SET setmcontext
#define GET getmcon... |
0Nera/BMOSP | 22,513 | kernel/cpu/idt_stubs.s | .text
.code64
.global isr_stubs
.extern isr_generic
common:
.align 16
subq $120, %rsp
movq %rbp, 0(%rsp)
movq %rbx, 8(%rsp)
movq %r15, 16(%rsp)
movq %r14, 24(%rsp)
movq %r13, 32(%rsp)
movq %r12, 40(%rsp)
movq %r11, 48(%rsp)
movq %r10, 56(%rsp)
movq %r9, 64(%... |
0Leeeezy0/20th_smart_vision | 7,618 | libraries/sdk/utilities/fsl_memcpy.S | /*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
.syntax unified
.text
.thumb
.align 2
#ifndef MSDK_MISC_OVERRIDE_MEMCPY
#define MSDK_MISC_OVERRIDE_MEMCPY 1
#endif
/*
This mempcy function is used to replace the GCC newlib function for these purpose... |
This dataset is a processed derivative of nick007x/github-code-2025.
The original data was aggregated by nick007x from public GitHub repositories. We have retained the original content, file paths, and metadata while restructuring the format for easier consumption by language-specific models.
To create this dataset, we performed the following processing on the source data:
.py, .rs, .ts) to their respective programming languages using a comprehensive extension map.The data contained in this dataset belongs to the original authors of the code repositories on GitHub.
nick007x/github-code-2025.If you use this dataset, please cite the original source:
@misc{github-code-2025,
author = {nick007x},
title = {GitHub Code 2025 Dataset},
year = {2025},
publisher = {Hugging Face},
howpublished = {\url{https://huggingface.co/datasets/nick007x/github-code-2025}}
}